Synchronization Overhead Reduction in Timed Cosimulation

Optimizing Timed Cosimulation by Hybrid Synchronization

Timed HW-SW cosimulation using native execution of OS and application SW

In SoC design, the software becomes more and more significant to meet short time-to-market constraints as well as to exploit its reprogrammability. Since most of SoC design cycle is spent in validation, designers need to have a fast validation of SW design to achieve a real reduction in design cycle. The SW validation needs also to be accurate in terms of SW timing and in the context of the ent...

Interface Design of VHDL Simulation for Hardware-Software Cosimulation

To perform cosimulation, an interface design of VHDL simulation is needed. This interface is responsible for communicating packets between any VHDL simulator and the cosimulation backplane, PeaCE, which is a Ptolemy extension as codesign environment. The interface also manages the simulation for correct timed cosimulation. By the automatic interface generation mechanism, the interface is genera...

Performance improvement of geographically distributed cosimulation by hierarchically grouped messages

To improve the performance of geographically distributed cosimulation, we propose a concept called hierarchically grouped message. The concept improves cosimulation performance, preserving the cosimulation accuracy, by hierarchically grouping messages transferred between simulators in a short period of simulated time into a single physical message, thereby reducing the number of physical messag...

Optimizing synchronization in multiprocessor DSP systems

This paper is concerned with multiprocessor implementations of embedded applications specified as iterative dataflow programs, in which synchronization overhead can be significant. We develop techniques to alleviate this overhead by determining a minimal set of processor synchronizations that are essential for correct execution. Our study is based in the context of self-timed execution of itera...